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VLSI Fault Modeling and Testing Techniques

Name: VLSI Fault Modeling and Testing Techniques
Brand: Praeger
SKU: 9780893917814
Price: 8514.00 INR
Availability: InStock
ISBN: 9780893917814

VLSI FAULT MODELING & TESTING

Contributor(s): Zobrist, George W. Author , Zobrist, George W. Editor Format: Hardback

Hardback · ISBN 9780893917814

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Key Specifications

ISBN	9780893917814
Subtitle	VLSI FAULT MODELING & TESTING
Publisher	Praeger
Publication date	January 1993
Language	English
MRP	£60.00 GBP
Page count	208
Item weight	92 g

VLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed.

VLSI Fault Modeling and Testing Techniques

Key Specifications

Zobrist, George W. Author

Zobrist, George W. Editor

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